SO instrumentation school: High level sinthesys for Xilinx FPGAs using Vivado HLS

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28/04/2021 to 30/04/2021
Introduction to high level sintesis tool Vivado HLS. This course shows sinthesis strategies, tool features, performance improvement, area optimization, interface creation, latency reduction testbench encoding, tricks and coding advices. It is updated to cover new tool features, and Vitis and Vivado HLx integration. Participants: 15 Prerequisite: Vivado 2020.2 installed (Webpack version is enough)